1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that performs gradation display using the combination of a plurality of subframes according to gradation levels expressed by a plurality of bits.
2. Description of the Related Art
Heretofore, a subframe driving method is known as one of halftone display methods in liquid crystal display devices. In a subframe driving method which is one type of time base modulation methods, a predetermined period (one frame that is a unit for display of one image in the case of moving pictures, for example) is divided into a plurality of subframes, and pixels are driven in a combination of subframes according to a gradation to be displayed. The gradation to be displayed is determined according to the ratio of a pixel drive period occupied in a predetermined period, and this ratio is specified by the combination of subframes.
In the liquid crystal display devices according to this subframe driving method, one is known in which pixels are individually configured of a master latch, a slave latch, a liquid crystal display element, and first to third switching transistors, which are three transistors in total (see Published Japanese Translation of PCT Patent Application No. 2001-523847, for example). In this pixel, one bit of a first data is applied to one input terminal of two input terminals of the master latch through the first switching transistor; a second data in the complementary relation with the first data is applied to the other input terminal through the second switching transistor; and when the pixel is selected by a row select signal applied through a row scanning line, the first data is written as the first and second switching transistors are turned to the ON-state. For example, when the first data has the logical value “1” and the second data has the logical value “0”, the pixel performs display.
After the data are written to all the pixels through the similar operations described above, the data that are written into the master latch are simultaneously read out to the slave latch as the third switching transistors of all the pixels are turned to the ON-state in the subframe period, and the data latched to the slave latch are applied from the slave latch to the pixel electrode of the liquid crystal display element. The operations above are then repeated for the individual subframes, and desired gradation display is performed with the combinations of all the subframes in a frame period.
Namely, in the liquid crystal display device according to the subframe driving method, the display periods of all the subframes in a frame period are pre-allocated to the same period or a different predetermined period. In the pixels, display is performed on all the subframes in the maximum gradation display; display is not performed on all the subframes in the minimum gradation display; and subframes for display are selected according to the gradation for display in a case where the other gradations are to be displayed. In the previous liquid crystal display device, input data is digital data expressing a gradation, which is also a digital driving technique with a two-stage latch configuration.
However, in the liquid crystal display device in the prior art, since the two latches in the pixels are configured of static random access memories (SRAMs), the number of transistors is increased and it is difficult to downsize the pixels. Moreover, Published Japanese Translation of PCT Patent Application No. 2001-523847 above does not disclose a specific circuit configuration of SRAMs and switching transistors that stably operates in a case where the two latches are configured of SRAMs.
The present invention is made in the viewpoints above, and there is a need to provide a liquid crystal display device that can downsize a pixel compared with a pixel using two SRAMs therein.
Moreover, there is another need to provide a liquid crystal display device including a pixel that can stably operate even in the configuration in which two SRAMs are provided in individual pixels.